View M58LW128H115ZA1_5957710.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1/65 product preview august 2003 this is preliminary information on a new product now in development. details are subject to change without notice. m58lw128h 128 mbit (8mb x16, uniform block, burst) 3v supply flash memory features summary n wide x16 data bus for high bandwidth n supply voltage Cv dd = 2.7 to 3.6v core supply voltage for pro- gram, erase and read operations Cv ddq = 1.8 to v dd for i/o buffers n synchronous/asynchronous read C synchronous burst read C asynchronous random read C asynchronous address latch controlled read C page read n access time C 8 or 16 word synchronous burst mode up to 66mhz C 8 word asynchronous page mode 115/25ns C random read 115ns n programming time C 32 word write buffer C 12s word effective programming time n 128 uniform 64 kword memory blocks n block protection C all blocks protected at power up C blocks can be protected individually and instantly Cwp for block lock-down n security Cv pen enabled data protection C 2 kbit protection register with 64 bit unique code in otp area n program and erase su spend n programmable wait signal n common flash interface n 100,000 program/erase cycles per block figure 1. packages n electronic signature C manufacturer code: 0020h C device code m58lw128h: 8802h fbga vfbga56 (zb) 11 x 9mm tbga64 (za) 10 x 13mm tbga
m58lw128h 2/65 table of contents summary description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. tbga64 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. vfbga56 connections (top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. block addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 address inputs (a1-a23). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 data inputs/outputs (dq0-dq15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 chip enable (e). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 output enable (g). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 write enable (w). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 reset/power-down (rp). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 latch enable (l). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 clock (k).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 wait (wait). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 status/(ready/busy) (sts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 program/erase enable (vpen). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 v ddq supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 v ssq ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 bus operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 address latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 bus read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 bus write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 output disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 power-down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 2. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 read modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 asynchronous read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 asynchronous latch controlled read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 asynchronous random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 asynchronous page read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 synchronous read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 synchronous burst read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 single synchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 read select bit (cr15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3/65 m58lw128h latency bits (cr14-cr11). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 wait polarity bit (cr10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 data output configuration bit (cr9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 wait configuration bit (cr8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 burst type bit (cr7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 valid clock edge bit (cr6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 burst length bit (cr2-cr0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3. configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. x-latency and data output configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. wait configuration example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 5. command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 read memory array command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 read query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 read status register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 clear status register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 word program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 write to buffer and program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 buffer enhanced factory program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 program and verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 set configuration register command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 block protect command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 block unprotect command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 block lock-down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 protection register program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 configure sts command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 6. standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 7. factory program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 table 8. configuration codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 9. read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 8. protection register locks and protection register memory map . . . . . . . . . . . . . . . . . 26 table 10. program, erase times and program erase endurance cycles . . . . . . . . . . . . . . . . . . 26 block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 reading a blocks protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 protected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 unprotected state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 lock-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
m58lw128h 4/65 protection operations during erase suspend. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 11. protection status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 program/erase controller status bit (sr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 erase suspend status bit (sr6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 erase status bit (sr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 program status bit (sr4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 v pen status bit (sr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 program suspend status bit (sr2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 block protection status bit (sr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 buffer enhanced factory program status bit (sr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 12. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 13. absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 14. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 9. ac measurement input output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 10. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 15. capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 16. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 11. single asynchronous random read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 12. single asynchronous latched controlled read ac waveforms . . . . . . . . . . . . . . . . . 36 figure 13. asynchronous page read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 17. asynchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 14. single synchronous burst read ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 15. 8 word synchronous burst read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 16. clock input ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 18. synchronous read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 17. asynchronous write ac waveform, write enable controlled . . . . . . . . . . . . . . . . . . . 41 figure 18. asynchronous read/write ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 19. asynchronous write/read ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 19. write ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 20. reset, power-down and power-up ac waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 20. reset, power-down and power-up ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 43 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 21. tbga64 10x13mm - 8x8 ball array, 1mm pitch, package outline . . . . . . . . . . . . . . . . 44 table 21. tbga64 10x13mm - 8x8 ball array, 1mm pitch, package mechanical data . . . . . . . . . 44 figure 22. vfbga56 11x9mm - 8x7 ball array, 0.75mm pitch, package outline . . . . . . . . . . . . . 45 table 22. vfbga56 11x9mm - 8x7 ball array, 0.75mm pitch, package mechanical data . . . . . . 45 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 23. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 appendix a. block address table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
5/65 m58lw128h table 24. block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 appendix b. common flash interface - cfi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 25. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 26. cfi - query address and data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 27. cfi - device voltage and timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 28. device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 29. block status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 30. extended query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 31. burst read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 appendix c. flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 23. write to buffer and program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . 54 figure 24. buffer enhanced factory program flowchart and pseudo code . . . . . . . . . . . . . . . . 55 figure 25. program suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . 56 figure 26. erase flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 27. erase suspend & resume flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . 58 figure 28. protection operations flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 29. protection register program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . 60 figure 30. command interface and program erase controller flowchart (a) . . . . . . . . . . . . . . . . 61 figure 31. command interface and program erase controller flowchart (b) . . . . . . . . . . . . . . . . 62 figure 32. command interface and program erase controller flowchart (c) . . . . . . . . . . . . . . . . 63 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 32. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
m58lw128h 6/65 summary description m58lw128h is a 128 mbit (8mb x16) non-volatile memory that can be read, erased and repro- grammed. these operations can be performed us- ing a single low voltage (2.7v to 3.6v) core supply. on power-up the memory defaults to read mode with an asynchronous bus where it can be read in the same way as a non-burst flash memory. the memory is divided into 128 blocks of 1mbit that can be erased independently so it is possible to preserve valid data while old data is erased. program and erase commands are written to the command interface of the memory. an on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are re- quired to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified in the status regis- ter. the command set required to control the memory is consistent with jedec standards. the device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. in asynchronous read mode an address latch input can be used to latch ad- dresses in latch controlled mode. in synchronous burst read mode, data is output on each clock cy- cle at frequencies of up to 66mhz. the write buffer allows the microprocessor to pro- gram from 1 to 32 words in parallel, both speeding up the programming and freeing up the micropro- cessor to perform other work. a word program command is available to program a single word. erase can be suspended in order to perform either read or program in any other block and then re- sumed. program can be suspended to read data in any other block and then resumed. each block can be programmed and erased over 100,000 cycles. the m58lw128h features an instant, individual block protection scheme that allows any block to be protected or unprotected with no latency, en- abling instant code and data protection. all blocks have three levels of protection. they can be pro- tected and locked-down individually preventing any accidental programming or erasure. there is an additional hardware protection against program and erase. when v pp v pplk all blocks are pro- tected against program or erase. all blocks are protected at power- up. the device includes a protection register and two protection register locks to increase the protec- tion of a systems design. the protection register is divided into seventeen 128-bit sub-registers: the first sub-register consists of a 64 bit segment con- taining a unique device number written by st, and a 64-bit segment one-time-programmable (otp) by the user. the other 16 sub-registers are all otp and available for the user to program. the user programmable segment and sub-registers can be permanently protected. the protection register locks can be permanently protected by the user. figure 8, shows the protection register locks and protection register memory map. the reset/power-down pin is used to apply a hardware reset to the memory and to set the de- vice in power-down mode. the sts signal is an open drain output that can be used to identify the program/erase controller sta- tus. it can be configured in two modes: ready/ busy mode where a static signal indicates the sta- tus of the p/e.c, and status mode where a pulsing signal indicates the end of a program or block erase operation. in status mode it can be used as a system interrupt signal, useful for saving cpu time. the memory is available in vfbga56 (11 x 9mm, 0.75mm pitch) and tbga64 (10 x 13mm, 1mm pitch) packages.
7/65 m58lw128h figure 2. logic diagram note: 1. the sts pin is available in tbga64 packages only and not in vfbga56 packages. see figures 3 and 4. table 1. signal names note: 1. the sts pin is available in tbga64 packages only and not in vfbga56 packages. see figures 3 and 4. ai06754 23 a1-a23 w dq0-dq15 v dd m58lw128h e v ss 16 g rp k v ddq v pen v ssq sts (1) l wait wp a1-a23 address inputs dq0-dq15 data inputs/outputs e chip enable g output enable k clock l latch enable wait wait sts (1) status/(ready/busy) rp reset/power-down v pen program/erase enable w write enable wp write protect v dd supply voltage v ddq input/output supply voltage v ss ground v ssq input/output ground nc not connected internally
m58lw128h 8/65 figure 3. tbga64 connections (top view through package) ai06755 dq6 a1 v ss v dd dq10 v dd dq7 dq5 v ddq dq2 h dq14 v ssq dq13 d a16 a20 e a9 c a17 a21 a11 a15 nc a8 b nc a19 a2 a13 a14 a 8 7 6 5 4 3 2 1 a7 a3 a4 a5 g f e dq0 nc a6 v pen a22 a18 a10 a12 rp dq15 sts dq9 dq8 dq1 dq4 dq3 g dq12 dq11 w v ss nc wp v ddq v ddq k a23 v ssq l wait nc nc
9/65 m58lw128h figure 4. vfbga56 connections (top view through package) ai06756 v ddq a12 dq13 a19 dq3 v dd dq5 dq8 d a23 a8 k a21 c a2 a3 wait w v ss v ss b a4 a6 a13 v pen a 8 7 6 5 4 3 2 1 a11 a14 a16 a15 g f e dq14 a9 v dd a5 a7 a22 l rp e a1 dq6 v ddq dq15 dq2 dq4 g dq10 dq11 v ssq a10 a18 a20 dq12 wp dq1 dq7 dq9 dq0 v ssq a17
m58lw128h 10/65 figure 5. block addresses note: also see appendix a, table 24 for a full listing of the block addresses ai06757 7fffffh 7f0000h 01ffffh 010000h 00ffffh 000000h word (x16) bus width 7effffh 7e0000h total of 128 1 mbit blocks 1 mbit or 64 kwords 1 mbit or 64 kwords 1 mbit or 64 kwords 1 mbit or 64 kwords
11/65 m58lw128h signal descriptions see figure 2, logic diagram and table 1, signal names, for a brief overview of the signals connect- ed to this device. address inputs (a1-a23). the address inputs are used to select the cells to access in the mem- ory array during bus read operations either to read or to program data to. during bus write oper- ations they control the commands sent to the command interface of the internal state machine. chip enable and latch enable must be low when selecting the addresses. the address latch is transparent when latch en- able is low, v il . the address is internally latched in an erase or program operation. data inputs/outputs (dq0-dq15). the data in- puts/outputs output the data stored at the selected address during a bus read operation, or are used to input the data during a program operation. dur- ing bus write operations they represent the com- mands sent to the command interface of the internal state machine. when used to input data or write commands they are latched on the rising edge of write enable or chip enable, whichever occurs first. when chip enable and output enable are both low, v il , the data bus outputs data from the mem- ory array, the electronic signature, the block pro- tection status, the cfi information or the contents of the status register. the data bus is high imped- ance when the chip is deselected, output enable is high, v ih, or the reset/power-down signal is low, v il . when the program/erase controller is active the ready/busy status is given on dq7. chip enable (e ). the chip enable, e , input acti- vates the memory control logic, input buffers, de- coders and sense amplifiers. chip enable, e , at v ih deselects the memory and reduces the power consumption to the standby level, i dd1 . output enable (g ). the output enable, g , gates the outputs through the data output buffers during a read operation. when output enable, g , is at v ih the outputs are high impedance. output enable, g , can be used to inhibit the data output during a burst read operation. write enable (w ). the write enable input, w , controls writing to the command interface, input address and data latches. both addresses and data can be latched on the rising edge of write en- able. write protect (wp ). write protect is an input that gives an additional hardware protection for each block. when write protect is at v il , the lock-down is enabled and the protection status of the locked- down blocks cannot be changed. when write pro- tect is at v ih , the lock-down is disabled and the locked-down blocks can be protected or unpro- tected. reset/power-down (rp ). the reset/power- down pin provides a hardware reset of the mem- ory. a hardware reset is achieved by holding reset/ power-down low, v il , for at least t plph . when reset/power-down is low, v il , the status regis- ter information is cleared, all blocks are locked down, the configuration register is reset and the power consumption is reduced to its power-down level. the device is deselected and outputs are high impedance. after reset/power-down goes high, v ih , the memory will be ready for bus read and bus write operations after t phqv . if reset/power-down goes low, v il , during an erase or program operation, the operation is abort- ed and the data may be corrupted. in this case the status/(ready/busy) pin stays low, v il , for a max- imum timing of t plsz, until the completion of the in- ternal reset operations. note that the status/ (ready/busy) pin does not fall during a reset (refer to status/(ready/busy) section for more details). latch enable (l ). the bus interface is config- ured to latch the address inputs on the rising edge of latch enable, l . in synchronous bus operations the address is latched on the active edge of the clock when latch enable is low, v il or on the ris- ing of latch enable, whichever occurs first. once latched, the addresses may change without affect- ing the address used by the memory. when latch enable is low, v il , the latch is transparent. clock (k). the clock, k, is used to synchronize the memory with the external bus during synchro- nous read operations. the clock can be config- ured to have an active rising or falling edge. bus signals are latched on the active edge of the clock during synchronous bus operations. in synchro- nous burst read mode the address is latched on the first active clock edge when latch enable is low, v il , or on the rising edge of latch enable, whichever occurs first. during asynchronous bus operations the clock is not used. wait (wait). wait is an output signal used dur- ing synchronous burst read to indicate whether the data on the output bus are valid. this output is high impedance when chip enable is at v ih or re- set is at v il . status/(ready/busy) (sts). the sts signal ex- ists in the tbga64 package only (not available in the vfbga56 package). it is an open drain output that can be used to identify the program/erase controller status. it can be configured in two modes:
m58lw128h 12/65 n ready/busy - the pin is low, v ol , during program and erase operations and high impedance when the memory is ready for any read, program or erase operation. n status - the pin gives a pulsing signal to indicate the end or the suspension of a program or block erase operation. after power-up or reset the sts pin is configured in ready/busy mode. the pin can be configured for status mode using the configure sts com- mand. when the program/erase controller is idle, or sus- pended, sts can float high through a pull-up re- sistor. the use of an open-drain output allows the sts pins from several memories to be connected to a single pull-up resistor (a low will indicate that one, or more, of the memories is busy). sts is not low during a reset unless the reset was applied when the program/erase controller was active. the status/(ready/busy) pin can rise be- fore reset/power-down rises. program/erase enable (v pen ). the program/ erase enable input, v pen, is used to protect all blocks, preventing program and erase operations from affecting their data. program/erase enable must be kept high during all program/erase controller operations, other- wise the operations is not guaranteed to succeed and data may become corrupt. v dd supply voltage. v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). v ddq supply voltage. v ddq provides the power supply to the i/o pins and enables all outputs to be powered independently from v dd . v ddq can be tied to v dd or can use a separate supply. it is recommended to power-up and power-down v dd and v ddq together to avoid any condition that would result in data corruption. v ss ground. ground, v ss, is the reference for the core power supply. it must be connected to the system ground. v ssq ground. v ssq ground is the reference for the input/output circuitry driven by v ddq . v ssq must be connected to v ss . note: each device in a system should have v dd and v ddq decoupled with a 0.1f ceramic capacitor close to the pin (high frequency, in- herently low inductance capacitors should be as close as possible to the package). see fig- ure 10, ac measurement load circuit.
13/65 m58lw128h bus operations there are six standard bus operations that control the device. these are address latch, bus read, bus write, output disable, power-down and standby. see table 2, bus operations, for a sum- mary. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus write operations. address latch. address latch operations input valid addresses. a valid bus operation involves setting the desired address on the address inputs, setting chip en- able and latch enable low, v il and keeping write enable high, v ih ; the address is latched on the ris- ing edge of address latch. bus read. bus read operations are used to out- put the contents of the memory array, the elec- tronic signature, the status register, the common flash interface and the block protection status. a valid bus operation involves setting the desired address on the address inputs, applying a low signal, v il , to chip enable, output enable and latch enable and keeping write enable high, v ih . according to the synchronous or asynchronous read mode selected, and to the data to be output, the wait signal will be either valid or driven (see table 2 for details). the data read depends on the previous command written to the memory (see command interface section). see figures 11, 12, 13, 14, 15 and 16 read ac waveforms, and tables 17 and 18 read ac characteristics, for details of when the output becomes valid. bus write. bus write operations write com- mands to the memory or latch addresses and input data to be programmed. a valid bus write operation begins by setting the desired address on the address inputs. the ad- dress inputs are latched by the command inter- face on the rising edge of chip enable or write enable, whichever occurs first. the data inputs/ outputs are latched by the command interface on the rising edge of chip enable or write enable, whichever occurs first. output enable must remain high, v ih , during the bus write operation. see figures 17, 18 and 19, write ac waveforms, and table 19, write ac characteristics, for details of the timing requirements. output disable. the data inputs/outputs are high impedance when the output enable is at v ih . power-down. the memory is in power-down mode when reset/power-down, rp , is low. the power consumption is reduced to the power-down level, i dd2 , and the outputs are high impedance, independent of chip enable, output enable or write enable. standby. standby disables most of the internal circuitry, allowing a substantial reduction of the current consumption. the memory is in standby when chip enable is at v ih . the power consump- tion is reduced to the standby level i dd1 and the outputs are set to high impedance, independently from the output enable or write enable inputs. if chip enable switches to v ih during a program or erase operation, the device enters standby mode when finished. table 2. bus operations note: 1. x = dont care v il or v ih . 2. depends on g operation e g w rp l wait a1-a23 dq0-dq15 address latch v il x v ih v ih v il driven address data output or hi-z (2) bus read synchronous read: memory array v il v il v ih v ih v il valid address data output asynchronous read, synchronous read: status register, cfi, electronic signature, block protection status v il v il v ih v ih v il driven address data output bus write v il v ih v il v ih x driven address data input output disable v il v ih v ih v ih x driven x high z power-down x x x v il x high z x high z standby v ih xx v ih x high z x high z
m58lw128h 14/65 read modes read operations can be performed in two different ways depending on the settings in the configura- tion register. if the clock signal is dont care for the data output, the read operation is asynchro- nous; if the data output is synchronized with clock, the read operation is synchronous. the read mode and format of the data output are determined by the configuration register. (see configuration register section for details). on power-up or after a hardware reset the mem- ory defaults to asynchronous read mode. asynchronous read modes in asynchronous read operations the clock signal is dont care. the device outputs the data corre- sponding to the address latched, that is the mem- ory array, status register, common flash interface, electronic signature or block protection status depending on the command issued. cr15 in the configuration register must be set to 1 for asynchronous operations. asynchronous read operations can be performed in three different ways, asynchronous latch con- trolled read, asynchronous random read and asynchronous page read. asynchronous latch controlled read. in a- synchronous latch controlled read operations read the address is latched in the memory before the value is output on the data bus, allowing the address to change during the cycle without affect- ing the address that the memory uses. a valid bus operation involves setting the desired address on the address inputs, setting chip en- able and latch enable low, v il and keeping write enable high, v ih ; the address is latched on the ris- ing edge of address latch. once latched, the ad- dress inputs can change. set output enable low, v il , to read the data on the data inputs/outputs; see figure 12, single asynchronous latch con- trolled read ac waveforms and table 17, asyn- chronous read ac characteristics, for details on when the output becomes valid. see figure 12, single asynchronous latch con- trolled read ac waveforms, and table 17, asyn- chronous read ac characteristics, for details. asynchronous random read. as the latch en- able input is transparent when set low, v il , asyn- chronous random read operations can be performed by holding latch enable low, v il throughout the bus operation. see figure 11, single asynchronous random read ac waveforms, and table 17, asynchro- nous read ac characteristics, for details. asynchronous page read. in asynchronous page read mode a page of data is internally read and stored in a page buffer. each memory page is 8 words and has the same a4-a23, only a1-a3 may change. the first read operation within the page has the normal access time (t avqv ), subsequent reads within the same page have much shorter access times (t avqv1 ). if the page changes then the nor- mal, longer timings apply again. see figures 13, asynchronous page read ac waveforms, and table 17, asynchronous read ac characteristics, for details. synchronous read modes in synchronous read mode the data output is syn- chronized with the clock. cr15 in the configura- tion register must be set to 0 for synchronous operations. synchronous burst read. in synchronous burst read mode the data is output in bursts syn- chronized with the clock. synchronous burst read mode can only be used to read the memory array. for other read opera- tions, such as read status register, read cfi, read electronic signature and block protection status, single synchronous read or asynchro- nous read must be used. in synchronous burst read mode the flow of the data output depends on parameters that are con- figured in the configuration register. a valid synchronous burst read operation begins when the address is set on the address inputs, write enable is high, v ih , and chip enable and latch enable are low, v il , during the active edge of the clock. the address is latched on the first ac- tive clock edge when latch enable is low, or on the rising edge of latch enable, whichever occurs first. the data becomes available for output after the x-latency specified in the burst control regis- ter has expired. the output buffers are activated by setting output enable low, v il . see figures 6 and 7 for examples of synchronous burst read operations. the number of words to be output during a syn- chronous burst read operation can be configured as 8 words, 16 words. only sequential burst is available. see table 18, synchronous read ac character- istics and figures 14 and 15, synchronous burst read ac waveform for details. single synchronous read. single synchro- nous read operations are similar to synchronous burst read operations except that only the first data output after the x latency is valid. single syn- chronous reads are used to read the status reg- ister, cfi, electronic signature and block protection status.
15/65 m58lw128h configuration register the configuration register is used to configure the type of bus access that the memory will per- form. the configuration register bits are de- scribed in table 3. they specify the selection of the burst length, burst type, burst latencies and the read operation. see figures 6 and 7 for examples of synchronous burst read configurations. the configuration register is set through the command interface and will retain its information until it is re-configured, the device is reset, or the device goes into reset/power-down mode. the configuration register is read using the read electronic signature command at address 05h. read select bit (cr15). the read select bit, cr15, is used to switch between asynchronous and synchronous read operations. when the read select bit is set to 1, read operations are asyn- chronous; when the read select bit is set to 0, read operations are synchronous. on reset or power-up the read select bit is set to 1 for asynchronous access. latency bits (cr14-cr11). the x-latency bits are used during synchronous read operations to set the number of clock cycles between the ad- dress being latched and the first data becoming available. for correct operation the latency bits can only assume the values in table 3, configura- tion register. wait polarity bit (cr10). in synchronous burst mode, the wait signal indicates whether the output data are valid or a wait state must be inserted. the wait polarity bit is used to set the polarity of the wait signal. when the wait polarity bit is set to 0, the wait signal is active low. when the wait polarity bit is set to 1 the wait signal is active high (default). data output configuration bit (cr9). the data output configuration bit determines whether the output remains valid for one or two clock cycle(s). when the data output configuration bit is 0 the output data is valid for one clock cycle, when the data output configuration bit is 1 the output data is valid for two clock cycles (default). the data output configuration depends on the condition: n t khkh > t khqv + t qvk_cpu where t khkh is the clock period, t qvk_cpu is the data setup time required by the system cpu and t khqv is the clock to data valid time. if this condi- tion is not satisfied, the data output configuration bit should be set to 1 (two clock cycles). refer to figure 6, x-latency and data output configura- tion example. wait configuration bit (cr8). in burst mode the wait configuration bit controls the timing of the wait output pin, wait. when wait is asserted, data is not valid and when wait is de-asserted, data is valid. when the wait configuration bit is 0 the wait output pin is de-asserted with valid da- ta. when the wait configuration bit is 1 (default) the wait output pin is de-asserted one clock cycle before valid data if data output configuration bit (cr9) is '0', or two clock cycle before valid data if cr9 bit is '1'. burst type bit (cr7). the burst type bit is used to configure the sequence of addresses read as sequential or interleaved. when the burst type bit is 0 the memory outputs from interleaved ad- dresses; when the burst type bit is 1 the memory outputs from sequential addresses. only sequen- tial burst type is supported. see table 4, burst type definition, for the sequence of addresses output from a given starting address in the 8 and 16 burst length mode (cr2-cr0). valid clock edge bit (cr6). the valid clock edge bit, cr6, is used to configure the active edge of the clock, k, during synchronous burst read operations. when the valid clock edge bit is 0 the falling edge of the clock is the active edge; when the valid clock edge bit is 1 the rising edge of the clock is active. burst length bit (cr2-cr0). the burst length bits set the maximum number of words that can be output during a synchronous burst read oper- ation. table 3, configuration register gives the valid combinations of the burst length bits that the memory accepts; tables 4, burst type definition, give the sequence of addresses output from a giv- en starting address for each length. cr5, cr4 and cr3 are reserved for future use.
m58lw128h 16/65 table 3. configuration register address bit mnemonic bit name reset value value description 16 cr15 read select 1 0 synchronous burst read 1 asynchronous read (default at power-up) 15 to 12 cr14-cr11 x-latency xxx 0000- 0001 reserved 0010 x-latency = 2 0011 x-latency = 3 0100 x-latency = 4 0101 x-latency = 5 0110 x-latency = 6 0111 x-latency = 7 1000 x-latency = 8 1001 x-latency = 9 1010 x-latency = 10 1011- 1111 reserved 11 cr10 wait polarity x 0 wait signal is active low 1 wait signal is active high (default) 10 cr9 data output configuration x 0 data is valid for one clock cycle 1 data is valid for two clock cycles 9cr8 wait configuration x 0 wait is de-asserted with valid data 1 wait is de-asserted one clock before valid data (default) 8 cr7 burst type x 0 interleaved (not supported) 1 sequential (default) 7cr6 valid clock edge x 0 falling clock edge 1 rising clock edge 6 to 4 cr5-cr3 reserved 3 to 1 cr2-cr0 burst length xxx 001 reserved 010 8 words 011 16 words 111 reserved
17/65 m58lw128h table 4. burst type definition figure 6. x-latency and data output configuration example starting address x8 sequential x16 sequential 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15 1 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0 2 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1 3 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2 4 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3 5 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4 6 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5 7 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6 ... C ... 14 C 14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13 15 C 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 ... C C ai06758 a23-a1 valid address k l dq15-dq0 valid data x-latency valid data tllqv tllkh tkhkh tqvk_cpu tqvk_cpu tkhqv 1st cycle 2nd cycle 3rd cycle 4th cycle note. settings shown: x-latency = 4, data output held for one clock cycle e tkhll
m58lw128h 18/65 figure 7. wait configuration example ai06759 a23-a1 valid address k l dq15-dq0 valid data wait cr8 = '0' cr10 = '0' wait cr8 = '1' cr10 = '0' valid data not valid valid data e wait cr8 = '0' cr10 = '1' wait cr8 = '1' cr10 = '1'
19/65 m58lw128h command interface all bus write operations to the memory are inter- preted by the command interface. commands consist of one or more sequential bus write oper- ations. the commands and their codes are sum- marized in tables 5, 6 and 7. refer to these tables in conjunction with the text descriptions be- low. after power-up or a reset operation the memory enters read mode. synchronous read operations and latch con- trolled read operations can only be used to read the memory array. the electronic signature, cfi or status register will be read in asynchronous mode or single synchronous burst mode. once the memory returns to read memory array mode the bus will resume the setting in the configuration register automatically. table 5. command codes read memory array command the read memory array command returns the memory to read mode. one bus write cycle is re- quired to issue the read memory array command and return the memory to read mode. once the command is issued the memory remains in read mode until another command is issued. in read mode bus read operations access the memory array. while the program/erase controller is executing a program, erase, block protect, block unprotect or block lock-down command the memory will not accept the read memory array command until the operation completes. read electronic signature command the read electronic signature command is used to read the manufacturer code, the device code, the block protection status, the configuration register and the protection register. one bus write cycle is required to issue the read electron- ic signature command. once the command is is- sued subsequent bus read operations read the manufacturer code, the device code, the block protection status, the configuration register or the protection register until another command is issued. refer to table 9, read electronic signa- ture and figure 8, protection register locks and protection register memory map, for information on the addresses. read query command the read query command is used to read data from the common flash interface (cfi) memory area. one bus write cycle is required to issue the read query command. once the command is is- sued subsequent bus read operations read from the common flash interface memory area. see appendix b, tables 25, 26, 27, 28, 29 and 30 for details on the information contained in the com- mon flash interface (cfi) memory area. read status register command the read status register command is used to read the status register. one bus write cycle is required to issue the read status register com- mand. once the command is issued subsequent bus read operations read the status register un- til another command is issued. the status register information is present on the output data bus (dq0-dq7) when both chip en- able and output enable are low, v il . see the section on the status register and table 12 for details on the definitions of the status reg- ister bits. clear status register command the clear status register command can be used to reset bits 1, 3, 4 and 5 in the status register hex code command 01h block protect confirm 03h set configuration register confirm 10h alternative word program setup 20h block erase setup 2fh block lock-down confirm 40h word program setup 50h clear status register 60h block protect setup, block unprotect setup, block lock down setup and set configuration register setup 70h read status register 80h buffer enhanced factory program setup 90h read electronic signature 98h read query b0h program/erase suspend b8h configure sts c0h protection register program d0h program/erase resume, block erase confirm, block unprotect confirm or write to buffer and program confirm, buffer enhanced factory program confirm e8h write to buffer and program ffh read memory array
m58lw128h 20/65 to 0. one bus write is required to issue the clear status register command. the bits in the status register are sticky and do not automatically return to 0 when a new com- mand is issued. if any error occurs then it is essen- tial to clear any error bits in the status register by issuing the clear status register command before attempting a new command. block erase command the block erase command can be used to erase a block. it sets all of the bits in the block to 1. all previous data in the block is lost. if the block is pro- tected then the erase operation will abort, the data in the block will not be changed and the status register will output the error. two bus write operations are required to issue the command; the second bus write cycle latches the block address in the internal state machine and starts the program/erase controller. once the command is issued subsequent bus read opera- tions read the status register. see the section on the status register for details on the definitions of the status register bits. during the erase operation the memory will only accept the read status register command and the program/erase suspend command. all other commands will be ignored. typical erase times are given in table 10. see appendix c, figure 26, block erase flow- chart and pseudo code, for a suggested flowchart on using the block erase command. word program command the word program command is used to program a single word in the memory array. two bus write operations are required to issue the command; the first write cycle sets up the word program com- mand, the second write cycle latches the address and data to be programmed in the internal state machine and starts the program/erase controller. if the block being programmed is protected an er- ror will be set in the status register and the oper- ation will abort without affecting the data in the memory array. the block must be unprotected us- ing the blocks unprotect command. write to buffer and program command the write to buffer and program command makes use of the devices 32-word write buffer to speed up programming. up to 32 words can be loaded into the write buffer. the write to buffer and program command dramatically reduces in- system programming time compared to the stan- dard non-buffered program command. up to 32 words can be loaded into the write buffer and programmed into the memory. for best per- formance the 32 words must be aligned (same a6-a23), otherwise double program time is re- quired. four successive steps are required to issue the command. 1. one bus write operation is required to set up the write to buffer and program command. is- sue the set up command with the selected memory block address where the program op- eration should occur (any address in the block where the values will be programmed can be used). any bus read operations will start to out- put the status register after the 1st cycle. 2. use one bus write operation to write the same block address along with the value n on the data inputs/output, where n+1 is the number of words to be programmed. 3. use n+1 bus write operations to load the ad- dress and data for each word into the write buffer. the address must be between start ad- dress and start address plus n, where start ad- dress is the first word address. 4. finally, use one bus write operation to issue the final cycle to confirm the command and start the program operation. if one address of the data pasts the block bound- aries or failing to follow the correct sequence of bus write cycles w ill set an error in the status register and abort the operation without affecting the data in the memory array. the status register should be cleared before re-issuing the command. if the block being programmed is protected an er- ror will be set in the status register and the oper- ation will abort without affecting the data in the memory array. the block must be unprotected us- ing the blocks unprotect command. see appendix c, figure 23, write to buffer and program flowchart and pseudo code, for a sug- gested flowchart on using the write to buffer and program command. buffer enhanced factory program command the buffer enhanced factory program command has been specially developed to speed up pro- gramming in manufacturing environments where the programming time is critical. it is used to program one or more write buffer(s) of 32 words to a block. once the device enters buffer enhanced factory program mode, the write buffer can be reloaded any number of times as long as the address remains within the same block. only one block can be programmed at a time. the use of the buffer enhanced factory program command requires certain operating conditions: n v pen must be set to v penh n v dd must be within operating range
21/65 m58lw128h n ambient temperature, t a must be 25c 5c n the targeted block must be unlocked n the start address must be aligned with the start of a 32 word buffer boundary n the address must remain the start address throughout programming. dual operations are not supported during the buff- er enhanced factory program operation and the command cannot be suspended. the buffer enhanced factory program command consists of three phases: the setup phase, the program and verify phase, and the exit phase, refer to table 7, factory program command and figure 24, buffer enhanced factory program flowchart. setup phase. the buffer enhanced factory pro- gram command requires two bus write cycles to initiate the command. n the first bus write cycle sets up the buffer enhanced factory program command. n the second bus write cycle confirms the command. after the confirm command is issued, read opera- tions output the contents of the status register. the read status register command must not be issued as it will be interpreted as data to program. the status register p/e.c. bit sr7 should be read to check that the p/e.c. is ready to proceed to the next phase. if an error is detected, sr4 goes high (set to 1) and the buffer enhanced factory program opera- tion is terminated. see status register section for details on the error. program and verify phase. the program and verify phase requires 32 bus write cycles to pro- gram the 32 words to the write buffer. the data is stored sequentially, starting at the first address of the write buffer, until the write buffer is full (32 words). to program less than 32 words, the re- maining data words should be filled with ffffh. three successive steps are required to issue and execute the program and verify phase of the com- mand. 1. use one bus write operation to latch the start address and the first word to be programmed. the status register bank write status bit sr0 should be read to check that the p/e.c. is ready for the next word. 2. each subsequent word to be programmed is latched with a new bus write operation. the address must remain the start address as the p/e.c. increments the address location.if any address that is not in the same block as the start address is given, the program and verify phase terminates. status register bit sr0 should be read between each bus write cycle to check that the p/e.c. is ready for the next word. 3. once the write buffer is full, the data is pro- grammed sequentially to the memory array. af- ter the program operation the device automatically verifies the data and reprograms if necessary. when the p/e.c. is busy no bus write operation can be performed. the program and verify phase can be repeated, without re-issuing the command, to program addi- tional 32 word locations as long as the address re- mains in the same block. 4. finally, after all words, or the entire block have been programmed, write one bus write opera- tion to any address outside the block containing the start address, to terminate program and verify phase. status register bit sr0 must be checked to deter- mine whether the program operation is finished. the status register may be checked for errors at any time but it must be checked after the entire block has been programmed. exit phase. status register p/e.c. bit sr7 set to 1 indicates that the device has exited the buffer enhanced factory program operation and re- turned to read status register mode. a full status register check should be done to ensure that the block has been successfully programmed. see the section on the status register for more details. for optimum performance the buffer enhanced factory program command should be limited to a maximum of 100 program/erase cycles per block. if this limit is exceeded the internal algorithm will continue to work properly but some degradation in performance is possible. typical program times are given in table 10. see appendix c, figure 24, buffer enhanced fac- tory program flowchart and pseudo code, for a suggested flowchart on using the buffer enhanced factory program command. program/erase suspend command the program/erase suspend comm and is used to pause a word program, write to buffer and pro- gram or erase operation. the command will only be accepted during a program or an erase opera- tion. it can be issued at any time during an erase operation but will only be accepted during a word program or write to buffer and program command if the program/erase controller is running. one bus write cycle is required to issue the pro- gram/erase suspend command and pause the program/erase controller. once the command is issued it is necessary to poll the program/erase controller status bit (sr7) to find out when the program/erase controller has paused; no other commands will be accepted until the program/
m58lw128h 22/65 erase controller has paused. after the program/ erase controller has paused, the memory will con- tinue to output the status register until another command is issued. during the polling period between issuing the pro- gram/erase suspend command and the program/ erase controller pausing it is possible for the op- eration to complete. once the program/erase controller status bit (sr7) indicates that the pro- gram/erase controller is no longer active, the pro- gram suspend status bit (sr2) or the erase suspend status bit (sr6) can be used to deter- mine if the operation has completed or is suspend- ed. for timing on the delay between issuing the program/erase suspend command and the pro- gram/erase controller pausing see table 10. during program/erase suspend the read memo- ry array, read status register, clear status reg- ister, read electronic signature, read query and program/erase resume commands will be ac- cepted by the command interface. additionally, if the suspended operation was erase then the write to buffer and program, and the program suspend commands will also be accepted. when a program operation is completed inside a block erase sus- pend the read memory array command must be issued to reset the device in read mode, then the erase resume command can be issued to com- plete the whole sequence. only the blocks not be- ing erased may be read or programmed correctly. see appendix c, figure 25, program suspend & resume flowchart and pseudo code, and figure 27, erase suspend & resume flowchart and pseudo code, for suggested flowcharts on using the program/erase suspend command. program/erase resume command the program/erase resume command can be used to restart the program/erase controller after a program/erase suspend operation has paused it. one bus write cycle is required to issue the pro- gram/erase resume command. once the com- mand is issued subsequent bus read operations read the status register. set configuration register command. the set configuration register command is used to write a new value to the configuration register (see table 3). two bus write cycles are required to issue the set configuration register command. once the command is issued the memory returns to read mode as if a read memory array com- mand had been issued. the value for the configuration register is pre- sented on a1-a16. cr0 is on a1, cr1 on a2, etc.; the other address bits are ignored. block protect command the block protect command is used to protect a block by setting the block protection status bit, thus preventing program or erase operations from changing the data in it. all blocks are protected at power-up or reset. two bus write cycles are required to issue the block protect command. n the first bus cycle sets up the block protect command. n the second bus write cycle latches the block address. the protection status can be monitored for each block using the read electronic signature com- mand. once set, the block protection status bit remains set until a hardware reset or power-down/power- up. it can be cleared by issuing a block unprotect command. refer to the section, block protection, for a detailed explanation. see appendix c, figure 28, protection operations flowchart and pseudo code, for a flowchart for using the block protect command. block unprotect command the block unprotect command is used to unpro- tect a block, allowing the block to be programmed or erased. two bus write cycles are required to issue the block unprotect command. n the first bus cycle sets up the block unprotect command. n the second bus write cycle latches the block address. the protection status can be monitored for each block using the read electronic signature com- mand. table 11 shows the protection status after issuing a block unprotect command. refer to the section, block protection, for a detailed explana- tion and appendix c, figure 28, protection opera- tions flowchart and pseudo code, for a flowchart for using the block unprotect command. block lock-down command a protected or unprotected block can be locked- down by issuing the block lock-down command. a locked-down block cannot be programmed or erased, or have its protection status changed when wp is low, v il . when wp is high, v ih, the lock-down function is disabled and the protected blocks can be individually unprotected by the block unprotect command. two bus write cycles are required to issue the block lock-down command. n the first bus cycle sets up the block protect command. n the second bus write cycle latches the block address. the protection status can be monitored for each block using the read electronic signature com-
23/65 m58lw128h mand. locked-down blocks revert to the protected (and not locked-down) state when the device is re- set on power-down. table 11 shows the protection status after issuing a block lock-down command. refer to the section, block protection, for a de- tailed explanation and appendix c, figure 28, pro- tection operations flowchart and pseudo code, for a flowchart for using the lock-down command. protection register program command the protection register program command is used to program the user segment of the protec- tion register. the segment is programmed 16 bits at a time. two write cycles are required to issue the protection register program command. n the first bus cycle sets up the protection register program command. n the second latches the address and the data to be written to the protection register and starts the program/erase controller. read operations output the status register con- tent after the programming has started. the user-programmable segment can be locked by programming bit 1 of the protection register lock location to 0. bit 0 of the protection register lock location locks the factory programmed seg- ment and is programmed to 0 in the factory. the locking of the protection register is not reversible, once the lock bits are programmed no further changes can be made to the values stored in the protection register, see figure 8, protection reg- ister memory map. attempting to program a previ- ously protected protection register will result in a status register error. the protection register program cannot be sus- pended. see appendix c, figure 29, protection register program flowchart and pseudo code, for the flowchart for using the protection register program command. configure sts command the configure sts command is available only in parts offered in the tfbga64 package. it is used to configure the status/(ready/busy) pin. after power-up or reset the sts pin is configured in ready/busy mode. the pin can be configured in status mode using the configure sts command (refer to status/(ready/busy) section for more de- tails). two write cycles are required to issue the config- ure sts command. n the first bus cycle sets up the configure sts command. n the second specifies one of the four possible configurations (refer to table 8, configuration codes): C ready/busy mode C pulse on erase suspended or complete C pulse on program suspended or complete C pulse on erase/ program suspended or com- plete the device will not accept the configure sts com- mand while the program/erase controller is busy or during program/erase suspend. when sts pin is pulsing it remains low for a typical time of 250ns. any invalid configuration code will set an error in the status register.
m58lw128h 24/65 table 6. standard commands note: 1. x dont care; ra read address, rd read data, ida identifier address, idd identifier data, srd status register data, pa p rogram address, pd program data, qa query address, qd query data, ba any address in the block, cr configuration register value, cc configuration code, pra protection register address, prd protection register data (see fig. 8). 2. for identifier addresses and data refer to table 9, read electronic signature. 3. for query address and data refer to appendix b, cfi. table 7. factory program command note: 1. wa=word address in targeted bank, pd=program data, ba=block address, x = dont care. 2. wa 1 is the start address, not ba 1 = not block address of wa 1 . 3. the program/verify phase can be executed any number of times as long as the data is to be programmed to the same block. 4. any address within the bank can be used. command cycles bus operations 1st cycle 2nd cycle subsequent final op. addr. data op. addr. data op. addr. data op. addr. data read memory array 3 2 write x ffh read ra rd read electronic signature 3 2 write x 90h read ida (3) idd (3) read status register 2 write x 70h read x srd read query 3 2 write x 98h read qa (4) qd (4) clear status register 1 write x 50h block erase 2 write x 20h write ba d0h word program 2 write x 40h 10h write pa pd write to buffer and program 4 + n write ba e8h write ba n write pa pd write x d0h program/erase suspend 1 write x b0h program/erase resume 1 write x d0h set configuration register 2 write x 60h write cr 03h block protect 2 write ba 60h write ba 01h block unprotect 2 write ba 60h write ba d0h block lock-down 2 write ba 60h write ba 2fh protection register program 2 write x c0h write pra prd configure sts command 2 write x b8h write x cc command phase cycles bus write operations 1st 2nd 3rd final -1 final add data add data add data add data add data buffer enhanced factory program setup 2 wa (4) 80h wa 1 d0h program/ verify (3) 3 32 wa 1 pd 1 wa 1 pd 2 wa 1 pd 3 wa 1 pd 31 wa 1 pd 32 exit 1 not ba 1 (2) x
25/65 m58lw128h table 8. configuration codes note: 1. dq2-dq7 are reserved 2. when sts pin is pulsing it remains low for a typical time of 250ns. table 9. read electronic signature note: 1. sba is the start base address of each block, cr is configuration register data, prd is protection register data. 2. base address, refer to figure 8 for more information. configuration code dq1 dq0 mode sts pin description 00h 0 0 ready/busy v ol during p/e operations hi-z when the memory is ready the sts pin is low during program and erase operations and high impedance when the memory is ready for any read, program or erase operation. 01h 0 1 pulse on erase suspended or complete pulse low then high when operation completed (2) supplies a system interrupt pulse at the end of a block erase operation. 02h 1 0 pulse on program suspended or complete supplies a system interrupt pulse at the end of a program operation. 03h 1 1 pulse on erase/ program suspended or complete supplies a system interrupt pulse at the end of a block erase or program operation. code address (a23-a1) data (dq15-dq0) manufacturer code 000000h 0020h device code 000001h 8802h block protection status protected sba+02h (1) 0001h unprotected 0000h protected and locked-down 0011h unprotected and locked-down 0010h configuration register 000005h cr protection register (2) protection register lock 0 000080h psr0 lock protection register lock 1 000089h psr1 lock protection sub-register 0 (psr0) 000081h to 000088h prd protection sub-registers 1 to 16 (psr1-psr16) 00008ah to 000109h prd
m58lw128h 26/65 figure 8. protection register locks and protection register memory map table 10. program, erase times and program erase endurance cycles note: 1. typical values measured at room temperature and nominal voltages. 2. sampled, but not 100% tested. 3. effective byte programming time 6s, effective word programming time 12s. 4. maximum value measured at worst case conditions for both temperature and v dd after 100,000 program/erase cycles. 5. maximum value measured at worst case conditions for both temperature and v dd . parameters m58lw128h unit min typ (1,2) max (2) block (1mb) erase 1 4 (4) s chip program (write to buffer) 83.9 252 (4) s chip erase time 128 512 (4) s program write buffer 320 960 s word/byte program time (word/byte program command) 150 450 (4) s buffered enhanced factory program time 288 864 s program suspend latency time 20 25 (5) s erase suspend latency time 20 25 (5) s program/erase cycles (per block) 100,000 cycles data retention 20 years ai08317 protection register lock 0 1 0 88h 81h 80h 89h protection sub-register 0 psr0 8ah 109h user programmable unique device number 84h 85h protection register lock 1 10 psr1 psr16 102h 91h user programmable user programmable 32 54 76 98 11 10 13 12 15 14
27/65 m58lw128h block protection the m58lw128h features an instant, individual block protection scheme that allows any block to be protected or unprotected with no latency. this protection scheme has three levels of protection. n protect/unprotect - this first level allows software-only control of block protection. n lock-down - this second level requires hardware interaction before the protection can be changed. n v pp v pplk - the third level offers a complete hardware protection against program and erase on all blocks. the protection status of each block can be set to protected, unprotected, and locked-down. table 11, defines all of the possible protection states (wp , dq1, dq0), and appendix c, figure 28, shows a flowchart for the protection operations. reading a blocks protection status the protection status of every block can be read in the read electronic signature mode of the device. to enter this mode write 90h to the device. subse- quent reads at the address specified in table 9, will output the protection status of that block. the protection status is represented by dq0 and dq1. dq0 indicates the block protect/unprotect status and is set by the block protect command and cleared by the block unprotect command. it is also automatically set when entering lock-down. dq1 indicates the lock-down status and is set by the lock-down command. it cannot be cleared by software, only by a hardware reset or power-down. the following sections explain the operation of the protection system. protected state the default status of all blocks on power-up or af- ter a hardware reset is protected (states (0,0,1) or (1,0,1)). protected blocks are fully protected from any program or erase. any program or erase oper- ations attempted on a protected block will return an error in the status register. the status of a protected block can be changed to unprotected or lock-down using the appropriate software com- mands. an unprotected block can be protected by issuing the block protect command. unprotected state unprotected blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. all unprotected blocks return to the protected state after a hard- ware reset or when the device is powered-down. the status of an unprotected block can be changed to protected or locked-down using the appropriate software commands. a protected block can be unprotected by issuing the block un- protect command. lock-down state blocks that are locked-down (state (0,1,x)) are protected from program and erase operations (as for protected blocks) but their protection status cannot be changed using software commands alone. a protected or unprotected block can be locked-down by issuing the block lock-down command. locked-down blocks revert to the pro- tected state when the device is reset or powered- down. the lock-down function is dependent on the wp input pin. when wp =0 (v il ), the blocks in the lock-down state (0,1,x) are protected from pro- gram, erase and protection status changes. when wp =1 (v ih ) the lock-down function is disabled (1,1,x) and locked-down blocks can be individual- ly unprotected to the (1,1,0) state by issuing the software command, where they can be erased and programmed. these blocks can then be re-pro- tected (1,1,1) and unprotected (1,1,0) as desired while wp remains high. when wp is low, blocks that were previously locked-down return to the lock-down state (0,1,x) regardless of any chang- es made while wp was high. device reset or pow- er-down resets all blocks, including those in lock- down, to the protected state. protection operations during erase suspend changes to block protection status can be per- formed during an erase suspend by using the standard protection command sequences to un- protect, protect or lock-down a block. this is useful in the case when another block needs to be updat- ed while an erase operation is in progress. to change the block protection during an erase operation, first write the erase suspend com- mand, then check the status register until it indi- cates that the erase operation has been suspended. next write the desired protect com- mand sequence to a block and the protection sta- tus will be changed. after completing any desired protection, read, or program operations, resume the erase operation with the erase resume com- mand. if a block is protected or locked-down during an erase suspend of the same block, the protection status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. protection operations cannot be per- formed during a program suspend.
m58lw128h 28/65 table 11. protection status note: 1. the protection status is defined by the write protect pin and by dq1 (1 for a locked-down block) and dq0 (1 for a pr otected block) as read in the read electronic signature command with a2 = v ih and a1 = v il . 2. all blocks are protected at power-up, so the default configuration is 001 or 101 according to wp status. 3. a wp transition to v ih on a protected block will restore the previous dq0 value, giving a 111 or 110. current protection status (1) (wp , dq1, dq0) next protection status (1) (wp , dq1, dq0) current state program/erase allowed after block protect command after block unprotect command after block lock-down command after wp transition 1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0 1,0,1 (2) no 1,0,1 1,0,0 1,1,1 0,0,1 1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0 0,0,1 (2) no 0,0,1 0,0,0 0,1,1 1,0,1 0,1,1 no 0,1,1 0,1,1 0,1,1 1,1,1 or 1,1,0 (3)
29/65 m58lw128h status register the status register provides information on the current or previous program, erase, block protect, block unprotect or block lock-down operation. the various bits in the status register convey in- formation and errors on the operation. they are output on dq7-dq0. to read the status register the read status reg- ister command can be issued. the status register is automatically read after program, erase, block protect, block unprotect, block lock-down and program/erase resume commands. the status register can be read from any address. the status register can only be read using asyn- chronous bus read or single synchronous read operations. once the memory returns to read memory array mode the bus will resume the set- ting in the configuration register automatically. the contents of the status register can be updat- ed during an erase or program operation by tog- gling the output enable pin or by dis-activating (chip enable, v ih ) and then reactivating (chip en- able and output enable, v il ) the device. status register bits sr5, sr4, sr3 and sr1 are associated with various error conditions and can only be reset with the clear status register com- mand. the status register bits are summarized in table 12, status register bits. refer to table 12 in conjunction with the following text descriptions. program/erase controller status bit (sr7). the program/erase controller status bit indicates whether the program/erase controller is active or inactive. when the program/erase controller sta- tus bit is low, v ol , the program/erase controller is active and all other status register bits are high impedance except during and after a buffer en- hanced factory program command (in this case sr0 isn't high impedance). when the bit is high, v oh , the program/erase controller is inactive. the program/erase controller status is low im- mediately after a program/erase suspend com- mand is issued until the program/erase controller pauses. after the program/erase controller paus- es the bit is high. during program, erase, block protect, block un- protect and block lock-down operations the pro- gram/erase controller status bit can be polled to find the end of the operation. the other bits in the status register should not be tested until the pro- gram/erase controller completes the operation and the bit is high. after the program/erase controller completes its operation the erase status, program status and block protection status bits should be tested for errors. erase suspend status bit (sr6). the erase suspend status bit indicates that an erase opera- tion has been suspended and is waiting to be re- sumed. the erase suspend status should only be considered valid when the program/erase con- troller status bit is high (program/erase controller inactive); after a program/erase suspend com- mand is issued the memory may still complete the operation rather than entering the suspend mode. when the erase suspend status bit is low, v ol , the program/erase controller is active or has com- pleted its operation. when the bit is high, v oh , a program/erase suspend command has been is- sued and the memory is waiting for a program/ erase resume command. when a program/erase resume command is is- sued the erase suspend status bit returns low. erase status bit (sr5). the erase status bit can be used to identify if the memory has failed to verify that the block has erased correctly. the erase status bit should be read once the program/ erase controller status bit is high (program/erase controller inactive). when the erase status bit is low, v ol , the mem- ory has successfully verified that the block has erased correctly or all blocks have been unprotect- ed successfully. when the erase status bit is high, v oh , the erase operation has failed. de- pending on the cause of the failure other status register bits may also be set to high, v oh . n if only the erase status bit (sr5) is set high, v oh , then the program/erase controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly. n if the failure is due to an erase with v pen low, v ol , then v pen status bit (sr3) is also set high, v oh . n if the failure is due to an erase on a protected block then block protection status bit (sr1) is also set high, v oh . n if the failure is due to a program or erase incorrect command sequence then program status bit (sr4) is also set high, v oh . once set high, the erase status bit can only be re- set low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. program status bit (sr4). the program status bit is used to identify a program or block protect failure. the program status bit should be read once the program/erase controller status bit is high (program/erase controller inactive).
m58lw128h 30/65 when the program status bit is low, v ol , the memory has successfully verified that the write buffer has programmed correctly or the block is protected. when the program status bit is high, v oh , the program has failed. depending on the cause of the failure other status register bits may also be set to high, v oh . n if only the program status bit (sr4) is set high, v oh , then the program/erase controller has applied the maximum number of pulses to the byte and still failed to verify that the write buffer has programmed correctly. n if the failure is due to a program or block protect with v pen low, v ol , then v pen status bit (sr3) is also set high, v oh . n if the failure is due to a program on a protected block then block protection status bit (sr1) is also set high, v oh . n if the failure is due to a program or erase incorrect command sequence then erase status bit (sr5) is also set high, v oh . once set high, the program status bit can only be reset low by a clear status register command or a hardware reset. if set high it should be reset be- fore a new program or erase command is issued, otherwise the new command will appear to fail. v pen status bit (sr3). the v pen status bit can be used to identify if a program, erase, block pro- tect or block unprotect operation has been at- tempted when v pen is low, v il . when the v pen status bit is low, v ol , no pro- gram, erase, block protect or block unprotect op- erations have been attempted with v pen low, v il , since the last clear status register command, or hardware reset. when the v pen status bit is high, v oh , a program, erase, block protect or block un- protect operation has been attempted with v pen low, v il . once set high, the v pen status bit can only be re- set by a clear status register command or a hard- ware reset. if set high it should be reset before a new program, erase, block protect or block un- protect command is issued, otherwise the new command will appear to fail. program suspend status bit (sr2). the pro- gram suspend status bit indicates that a program operation has been suspended and is waiting to be resumed. the program suspend status should only be considered valid when the program/erase controller status bit is high (program/erase con- troller inactive); after a program/erase suspend command is issued the memory may still complete the operation rather than entering the suspend mode. when the program suspend status bit is low, v ol , the program/erase controller is active or has completed its operation; when the bit is high, v oh , a program/erase suspend command has been is- sued and the memory is waiting for a program/ erase resume command. when a program/erase resume command is is- sued the program suspend status bit returns low. block protection status bit (sr1). the block protection status bit can be used to identify if a program or erase operation has tried to modify the contents of a protected block. when the block protection status bit is low, v ol , no program or erase operations have been at- tempted to protected blocks since the last clear status register command or hardware reset. when the block protection status bit is high, v oh , a program (sr4 set high) or erase (sr5 set high) operation has been attempted on a protected block. once set high, the block protection status bit can only be reset low by a clear status register com- mand or a hardware reset. if set high it should be reset before a new program or erase command is issued, otherwise the new command will appear to fail. buffer enhanced factory program status bit (sr0). the buffer enhanced factory program status bit can be used to check the progress of buffer enhanced factory program operations. sr0 high, v oh , indicates that the operation is in progress. sr0 low, v ol , indicates that the opera- tion has completed. for all other operations, sr0 is low, v ol , when p.e/c. is ready, otherwise sr0 is high imped- ance.
31/65 m58lw128h table 12. status register bits note: 1. sts configuration code is 00h, the device is in ready/busy mode. operation sr7 sr 6 sr5 sr4 sr3 sr2 sr1 sr0 sts (1) result (hex) program/erase controller active 0 hi-z v ol n/a write buffer not ready 0 hi-z v ol n/a write buffer ready 1 0 0 0 0 0 0 0 hi-z 80h write buffer ready in erase suspend 1 1 0 0 0 0 0 0 hi-z c0h write buffer ready, device busy in buffer enhanced factory program 0 0 0 0 0 0 0 0 hi-z 00h write buffer is not available, device is busy in buffer enhanced factory program 0 0 0 0 0 0 0 1 hi-z n/a program suspended 1 0 0 0 0 1 0 0 hi-z 84h program suspended in erase suspend 1 1 0 0 0 1 0 0 hi-z c4h program/block protect completed successfully 1 0 0 0 0 0 0 0 hi-z 80h program completed successfully in erase suspend 1 1 0 0 0 0 0 0 hi-z c0h program/block protect failure due to incorrect command sequence 1 0 1 1 0 0 0 0 hi-z b0h program failure due to incorrect command sequence in erase suspend 1 1 1 1 0 0 0 0 hi-z f0h program/block protect failure due to v pen error 1 0 0 1 1 0 0 0 hi-z 98h program failure due to v pen error in erase suspend 1 1 0 1 1 0 0 0 hi-z d8h program failure due to block protection 1 0 0 1 0 0 1 0 hi-z 92h program failure due to block protection in erase suspend 1 1 0 1 0 0 1 0 hi-z d2h program/block protect failure due to cell failure 1 0 0 1 0 0 0 0 hi-z 90h program failure due to cell failure in erase suspend 1 1 0 1 0 0 0 0 hi-z d0h erase suspended 1 1 0 0 0 0 0 0 hi-z c0h erase/blocks unprotect completed successfully 1 0 0 0 0 0 0 0 hi-z 80h erase/blocks unprotect failure due to incorrect command sequence 1 0 1 1 0 0 0 0 hi-z b0h erase/blocks unprotect failure due to v pen error 1 0 1 0 1 0 0 0 hi-z a8h erase failure due to block protection 1 0 1 0 0 0 1 0 hi-z a2h erase/blocks unprotect failure due to failed cells in block 1 0 1 0 0 0 0 0 hi-z a0h
m58lw128h 32/65 maximum rating stressing the device above the ratings listed in ta- ble 13, absolute maximum ratings, may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 13. absolute maximum ratings symbol parameter value unit min max t bias temperature under bias C40 125 c t stg storage temperature C55 150 c v io input or output voltage C0.6 v ddq +0.6 v v dd , v ddq supply voltage C0.6 5.0 v
33/65 m58lw128h dc and ac parameters this section summarizes the operating and mea- surement conditions, and the dc and ac charac- teristics of the device. the parameters in the dc and ac characteristics tables that follow, are de- rived from tests performed under the measure- ment conditions summarized in table 14, operating and ac measurement conditions. de- signers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. table 14. operating and ac measurement conditions figure 9. ac measurement input output waveform figure 10. ac measurement load circuit table 15. capacitance note: 1. t a = 25c, f = 1 mhz 2. sampled only, not 100% tested. parameter m58lw128h units 115 min max supply voltage (v dd ) 2.7 3.6 v input/output supply voltage (v ddq ) 1.8 v dd v ambient temperature (t a ) grade 1 0 70 c grade 6 C40 85 c load capacitance (c l ) 30 pf clock rise and fall times 3 ns input rise and fall times 4 ns input pulses voltages 0 to v ddq v input and output timing ref. voltages 0.5 v ddq v ai00610 v ddq 0v 0.5 v ddq ai03459 1.3v dq s c l c l includes jig capacitance 3.3k w 1n914 device under test 0.1f v dd v ddq 0.1f symbol parameter test condition typ max unit c in input capacitance v in = 0v 68pf c out output capacitance v out = 0v 812pf
m58lw128h 34/65 table 16. dc characteristics symbol parameter test condition min max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 5 a i dd supply current (random read) e = v il , g = v ih , f add = 6mhz 20 ma i ddb supply current (burst read) e = v il , g = v ih , f clock = 50mhz 30 ma i dd1 supply current (standby) e = v ih , rp = v ih 40 m a i dd2 supply current (reset/power-down) rp = v il 40 a i dd3 supply current (program or erase, block protect, block unprotect, block lock-down) program or erase operation in progress 30 ma i dd4 supply current (erase/program suspend) e = v ih 40 a v il input low voltage C0.5 v ddq x 0.3 v v ih input high voltage v ddq x 0.7 v ddq + 0.5 v v ol output low voltage i ol = 100a 0.2 v v oh output high voltage i oh = C100a v ddq C0.2 v v lko v dd lock-out voltage 2v v pplk v pp lock-out voltage 1v
35/65 m58lw128h figure 11. single asynchronous random read ac waveforms a1-a23 address valid l e g wait output valid dq0-dq15 ai06760 tavqv tavav tglqv telqv telqx rp tphqv tehqz tghqz tehtz hi-z tehqx tglqx
m58lw128h 36/65 figure 12. single asynchronous latched controlled read ac waveforms figure 13. asynchronous page read ac waveforms a4-a23 address valid l e g wait output valid dq0-dq15 ai06761 tavqv tavav tglqv telqv telqx tehqz tghqz tehtz hi-z tehqx tglqx valid a1-a3 address valid valid tlhax tavlh tlhll telth taxqx a4-a23 address valid l e g wait dq0-dq15 ai06762 tavqv tglqv telqv telqx tehqz tghqz tehtz hi-z tavqv1 tglqx valid a1-a3 address valid valid tlhax tavlh tlhll telth valid valid data 0 tavqv1 data 1 data 6 data 7
37/65 m58lw128h table 17. asynchronous read ac characteristics note: 1. for devices configured in word read mode t avqv1 = t avqv . 2. g may go low up to t elqv - t glqv after e goes low without any impact on t elqv . 3. sampled, not 100% tested. 4. the address remains valid in synchronous burst mode during t khax or t lhax , whichever timing is satisfied first. 5. refer only to address a1-a3 if l is not active otherwise to a1-a23. symbol alt parameter m58lw128h unit 115 v dd 2.7v to 3.3v 2.7v to 3.6v v ddq 1.65v to 1.95v 2.375v to 3.6v read timings t avav t rc address valid to next address valid min 115 115 ns t av qv (1) t acc address valid to output valid (random) max 115 115 ns t av qv 1 (1) t page address valid to output valid (page) max 30 25 ns t elqv t ce chip enable low to output valid max 115 115 ns t elqx t lz chip enable low to output transition min 0 0 ns t ehqx (3) t oh chip enable high to output transition min 0 0 ns t ehqz (3) t hz chip enable high to output hi-z max 25 25 ns t glqv (2) t oe output enable low to output valid max 30 25 ns t glqx (2) t olz output enable low to output transition min 0 0 ns t ghqx (3) t oh output enable high to output transition min 0 0 ns t ghqz (3) t df output enable high to output hi-z max 25 25 ns t phqv rp high to output valid max 190 180 ns latch timings t av lh t avadvh address valid to latch enable high min 9 7 ns t ellh t eladvh chip enable low to latch enable high min 9 7 ns t lhax (4) t advhax latch enable high to address transition min 10 8 ns t lhll t advhadvl latch enable high to latch enable low min 12 10 ns t lllh t advladvh latch enable pulse width min 12 10 ns t llqv t advlqv latch enable low to output valid (random) max 115 115 ns t axqx address change to output transition (5) min 0 0 ns
m58lw128h 38/65 figure 14. single synchronous burst read ac waveform k a1-a23 l e g wait dq0-dq15 ai06763 output valid tavkh tkhax address valid tavqv tlhll tavlh tlhax tlllh telkh tellh tglqv telqv tglqx teltl tkhqv tkhqx tehqz tghqz tehtz latency count tkhth
39/65 m58lw128h figure 15. 8 word synchronous burst read ac waveforms note: asynchronous read cr15 = 1 figure 16. clock input ac waveform k a1-a23 l e g wait dq0-dq15 ai06764 add. valid tavav tavlh tlhax telqv tglqx teltl tehqz tghqz tehtz latency count note 1 data 0 data 1 data 6 data 7 tkhqv tkhqx tkhqx tkhqv telqx tglqv tlhll tavqv tkhqv ai06981 tkhkh tf tr tkhkl tklkh
m58lw128h 40/65 table 18. synchronous read ac characteristics note: 1. the address remains valid in synchronous burst mode during t khax or t lhax , whichever timing is satisfied first. 2. the clock duty cycle should be around 50%. 3. applies only to subsequent synchronous read cycles. symbol alt parameter m58lw128h unit 115 v dd 2.7v to 3.3v 2.7v to 3.6v v ddq 1.65v to 1.95v 2.375v to 3.6v synchronous read timings t avk h t av clkh address valid to clock high min 9 7 ns t elkh t elclkh chip enable low to clock high min 9 7 ns t eltl (2) t elth chip enable low to wait low chip enable low to wait high max 30 25 ns t ehtz chip enable high to wait hi-z max 30 25 ns t khax (1) t clkhax clock high to address transition min 10 8 ns t khll clock high to latch enable low min 3 3 ns t khqv (2) t clkhqv clock high to output valid clock high to wait valid max 15 13 ns t khqx t clkhqx clock high to output transition clock high to wait transition min 3 3 ns t khth (3) clock high to wait high max 15 13 ns t llkh latch enable low to clock high min 9 7 ns clock specifications t khkh (2) t clk clock period (f = 50mhz) min 20 ns clock period (f = 66mhz) min 15 ns t khkl (2) t klkh clock high to clock low clock low to clock high min 7 4.5 ns t f (2) t r clock fall or rise time max 3 3 ns
41/65 m58lw128h figure 17. asynchronous write ac waveform, write enable controlled figure 18. asynchronous read/write ac waveform ai06765 dq0-dq15 rp w a1-a23 e g valid twheh tavwh telwl twhax tdvwh valid tavwh twhax telwl twheh twlwh twlwh twhwl twhdz tdvwh twhdz twhdz input data input data ai06766 dq0-dq15 rp g a1-a23 e w valid tehqz tavqv telqv valid tavwh twhax tglqv tdvwh twhdz tphdv output data input data tavav tglqx telqx tehqx tghqz telwl twlwh twheh
m58lw128h 42/65 figure 19. asynchronous write/read ac waveform table 19. write ac characteristics note: 1. for other parameters please refer to table 17, asynchronous read ac characteristics. 2. read operations can be initiated and terminated by either e or w . 3. sampled, not 100% tested. symbol parameter m58lw128h unit 115 v dd 2.7v to 3.3v 2.7v to 3.6v v ddq 1.65v to 1.95v 2.375v to 3.6v t avwh address valid to write enable high min 55 55 ns t dvwh data valid to write enable high min 60 60 ns t elwl chip enable low to write enable low min 0 0 ns t phwl (2) rp high to write enable low min 190 180 ns t whax write enable high to address transition min 0 0 ns t whdz write enable high to data hi-z min 0 0 ns t wheh write enable high to chip enable high min 0 0 ns t whwl write enable high to write enable low min 35 30 ns t wlwh (3) write enable low to write enable high min 60 60 ns t whgl write recovery before read min 35 35 ns ai06767 dq0-dq15 rp w a1-a23 e g valid twheh tavwh telwl valid tavav twlwh tavqv telqv tphwl input data output data tdvwh twhax twhgl tglqv twhdz tehqx tghqz tehqz
43/65 m58lw128h figure 20. reset, power-down and power-up ac waveform note: 1. sts configuration code is 00h, the device is in ready/busy mode. table 20. reset, power-down and power-up ac characteristics symbol parameter m58lw128h unit 115 t phqv reset/power-down high to data valid max 190 ns t plph reset/power-down low to reset/power-down high min 100 ns t vdhph supply voltages high to reset/power-down high min 60 s t plsz reset/power-down low to status(ready/busy) high impedance (end of the internal reset procedure device reset during program) max 20 s reset/power-down low to status(ready/busy) high impedance (end of the internal reset procedure device reset during erase) max 20 s ai06768c rp vdd, vddq tvdhph tplph power-up and reset device reset during program or erase dq0-dq15 tphqv tplsz sts (1) hi z hi z
m58lw128h 44/65 package mechanical figure 21. tbga64 10x13mm - 8x8 ball array, 1mm pitch, package outline note: drawing is not to scale. table 21. tbga64 10x13mm - 8x8 ball array, 1mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.300 0.200 0.350 0.0118 0.0079 0.0138 a2 0.800 0.0315 b 0.350 0.500 0.0138 0.0197 d 10.000 9.900 10.100 0.3937 0.3898 0.3976 d1 7.000 0.2756 ddd 0.100 0.0039 e 1.000 0.0394 e 13.000 12.900 13.100 0.5118 0.5079 0.5157 e1 7.000 0.2756 fd 1.500 0.0591 fe 3.000 0.1181 sd 0.500 0.0197 se 0.500 0.0197 e1 e d1 d eb sd se a2 a1 a bga-z23 ddd fd fe ball "a1"
45/65 m58lw128h figure 22. vfbga56 11x9mm - 8x7 ball array, 0.75mm pitch, package outline note: drawing is not to scale. table 22. vfbga56 11x9mm - 8x7 ball array, 0.75mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.000 0.0394 a1 0.150 0.0059 a2 0.660 0.0260 b 0.350 0.300 0.400 0.0138 0.0118 0.0157 d 11.000 10.900 11.100 0.4331 0.4291 0.4370 d1 5.250 0.2067 ddd 0.100 0.0039 e 9.000 8.900 9.100 0.3543 0.3504 0.3583 e1 4.500 0.1772 e 0.750 C C 0.0295 C C fd 2.875 0.1132 fe 2.250 0.0886 sd 0.375 0.0148 e1 e d a2 a1 a bga-z49 ddd e sd ball "a1" fe fd b d1
m58lw128h 46/65 part numbering table 23. ordering information scheme note: devices are shipped from the factory with the memory content bits erased to 1. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m58lw128h 115 za 6 t device type m58 architecture l = page mode, burst operating voltage w = v dd = 2.7v to 3.6v; v ddq = 1.8 to v dd device function 128h = 128 mbit (x16), uniform block, burst speed 115 = 115ns package za = tbga64 10 x 13mm, 1mm pitch zb = vfbga56 11 x 9mm, 0.75mm pitch temperature range 1 = 0 to 70 c 6 = C40 to 85 c option blank = standard packing t = tape & reel packing e = lead-free package, standard packing f = lead-free package, tape & reel packing
47/65 m58lw128h appendix a. block address table table 24. block addresses block number address range (x16 bus width) 128 7f0000h-7fffffh 127 7e0000h-7effffh 126 7d0000h-7dffffh 125 7c0000h-7cffffh 124 7b0000h-7bffffh 123 7a0000h-7affffh 122 790000h-79ffffh 121 780000h-78ffffh 120 770000h-77ffffh 119 760000h-76ffffh 118 750000h-75ffffh 117 740000h-74ffffh 116 730000h-73ffffh 115 720000h-72ffffh 114 710000h-71ffffh 113 700000h-70ffffh 112 6f0000h-6fffffh 111 6e0000h-6effffh 110 6d0000h-6dffffh 109 6c0000h-6cffffh 108 6b0000h-6bffffh 107 6a0000h-6affffh 106 690000h-69ffffh 105 680000h-68ffffh 104 670000h-67ffffh 103 660000h-66ffffh 102 650000h-65ffffh 101 640000h-64ffffh 100 630000h-63ffffh 99 620000h-62ffffh 98 610000h-61ffffh 97 600000h-60ffffh 96 5f0000h-5fffffh 95 5e0000h-5effffh 94 5d0000h-5dffffh 93 5c0000h-5cffffh 92 5b0000h-5bffffh 91 5a0000h-5affffh 90 590000h-59ffffh 89 580000h-58ffffh 88 570000h-57ffffh 87 560000h-56ffffh 86 550000h-55ffffh 85 540000h-54ffffh 84 530000h-53ffffh 83 520000h-52ffffh 82 510000h-51ffffh 81 500000h-50ffffh 80 4f0000h-4fffffh 79 4e0000h-4effffh 78 4d0000h-4dffffh 77 4c0000h-4cffffh 76 4b0000h-4bffffh 75 4a0000h-4affffh 74 490000h-49ffffh 73 480000h-48ffffh 72 470000h-47ffffh 71 460000h-46ffffh 70 450000h-45ffffh 69 440000h-44ffffh 68 430000h-43ffffh 67 420000h-42ffffh 66 410000h-41ffffh 65 400000h-40ffffh 64 3f0000h-3fffffh block number address range (x16 bus width)
m58lw128h 48/65 block number address range (x16 bus width) 63 3e0000h-3effffh 62 3d0000h-3dffffh 61 3c0000h-3cffffh 60 3b0000h-3bffffh 59 3a0000h-3affffh 58 390000h-39ffffh 57 380000h-38ffffh 56 370000h-37ffffh 55 360000h-36ffffh 54 350000h-35ffffh 53 340000h-34ffffh 52 330000h-33ffffh 51 320000h-32ffffh 50 310000h-31ffffh 49 300000h-30ffffh 48 2f0000h-2fffffh 47 2e0000h-2effffh 46 2d0000h-2dffffh 45 2c0000h-2cffffh 44 2b0000h-2bffffh 43 2a0000h-2affffh 42 290000h-29ffffh 41 280000h-28ffffh 40 270000h-27ffffh 39 260000h-26ffffh 38 250000h-25ffffh 37 240000h-24ffffh 36 230000h-23ffffh 35 220000h-22ffffh 34 210000h-21ffffh 33 200000h-20ffffh 32 1f0000h-1fffffh 31 1e0000h-1effffh 30 1d0000h-1dffffh 29 1c0000h-1cffffh 28 1b0000h-1bffffh 27 1a0000h-1affffh 26 190000h-19ffffh 25 180000h-18ffffh 24 170000h-17ffffh 23 160000h-16ffffh 22 150000h-15ffffh 21 140000h-14ffffh 20 130000h-13ffffh 19 120000h-12ffffh 18 110000h-11ffffh 17 100000h-10ffffh 16 0f0000h-0fffffh 15 0e0000h-0effffh 14 0d0000h-0dffffh 13 0c0000h-0cffffh 12 0b0000h-0bffffh 11 0a0000h-0affffh 10 090000h-09ffffh 9 080000h-08ffffh 8 070000h-07ffffh 7 060000h-06ffffh 6 050000h-05ffffh 5 040000h-04ffffh 4 030000h-03ffffh 3 020000h-02ffffh 2 010000h-01ffffh 1 000000h-00ffffh block number address range (x16 bus width)
49/65 m58lw128h appendix b. common flash interface - cfi the common flash interface is a jedec ap- proved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the mem- ory. the system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. when the cfi query command (rcfi) is issued the device enters cfi query mode and the data structure is read from the memory. tables 25, 26, 27, 28, 29 and 30 show the addresses used to re- trieve the data. table 25. query structure overview note: 1. offset 15h defines p which points to the primary algorithm extended query address table. 2. offset 19h defines a which points to the alternate algorithm extended query address table. 3. sba is the start base address for each block. table 26. cfi - query address and data output note: 1. query data are always presented on dq7-dq0. dq15-dq8 are set to '0'. 2. offset 19h defines a which points to the alternate algorithm extended query address table. offset sub-section name description 00h manufacturer code 01h device code 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing and voltage information 27h device geometry definition flash memory layout p(h) (1) primary algorithm-specific extended query table additional information specific to the primary algorithm (optional) a(h) (2) alternate algorithm-specific extended query table additional information specific to the alternate algorithm (optional) (sba+02)h block status register block-related information address a23-a1 data instruction 10h 51h "q" 51h; "q" query ascii string 52h; "r" 59h; "y" 11h 52h "r" 12h 59h "y" 13h 01h primary vendor: command set and control interface id code 14h 00h 15h 31h primary algorithm extended query address table: p(h) 16h 00h 17h 00h alternate vendor: command set and control interface id code 18h 00h 19h 00h alternate algorithm extended query address table 1ah (2) 00h
m58lw128h 50/65 table 27. cfi - device voltage and timing specification note: 1. bits are coded in binary code decimal, bit7 to bit4 are scaled in volts and bit3 to bit0 in 100mv. 2. bit7 to bit4 are coded in hexadecimal and scaled in volts while bit3 to bit0 are in binary code decimal and scaled in 100mv. 3. not supported. table 28. device geometry definition address a23-a1 data description 1bh 27h (1) v dd min, 2.7v 1ch 36h (1) v dd max, 3.6v 1dh 00h (2) v pp min C not available 1eh 00h (2) v pp max C not available 1fh 04h 2 n s typical time-out for word, dword prog C not available 20h 09h 2 n s, typical time-out for max buffer write 21h 0ah 2 n ms, typical time-out for erase block 22h 00h (3) 2 n ms, typical time-out for chip erase C not available 23h 02h 2 n x typical for word dword time-out max C not available 24h 02h 2 n x typical for buffer write time-out max 25h 02h 2 n x typical for individual block erase time-out maximum 26h 00h (3) 2 n x typical for chip erase max time-out C not available address a23-a1 data description 27h 18h n where 2 n is number of bytes memory size 28h 01h device interface 29h 00h organization sync./async. 2ah 06h maximum number of bytes in write buffer, 2 n 2bh 00h 2ch 01h bit7-0 = number of erase block regions in device 2dh 7fh number (n-1) of erase blocks of identical size; n=64 2eh 00h 2fh 00h erase block region information x 256 bytes per erase block (128k bytes) 30h 02h
51/65 m58lw128h table 29. block status register note: 1. ba specifies the first block address location, a23-a1. address a23-a1 data selected block information (ba+2)h (1) bit0 0 block unprotected 1 block protected bit1 0 block locked down 1 block locked down bit7-2 0 reserved for future features
m58lw128h 52/65 table 30. extended query information note: 1. query data are always presented on dq7-dq0. dq15-dq8 are set to '0'. 2. bits are coded in binary code decimal, bit7 to bit4 and scaled in volts while bit3 to bit0 are scaled in 100mv. address offset address a23-a1 data (hex) x16 bus width description (p)h 31h 50h "p" query ascii string - extended table (p+1)h 32h 52h "r" (p+2)h 33h 49h "i" (p+3)h 34h 31h major version number (p+4)h 35h 31h minor version number (p+5)h 36h e6h optional feature: (1=yes, 0=no) bit0, chip erase supported (0=no) bit1, suspend erase supported (1=yes) bit2, suspend program supported (1=yes) bit3, legacy block protect/unprotect supported (0=no) bit4, queue erase supported (0=no) bit5, instant individual block protection (1=yes) bit6, protection bits supported (1=yes) bit7, page read supported (1=yes) bit8, synchronous read supported (1=yes) bits 9 to 31 reserved for future use (p+6)h 37h 01h (p+7)h 38h 00h (p+8)h 39h 00h (p+9)h 3ah 01h function allowed after suspend: program allowed after erase suspend (1=yes) bit 7-1 reserved for future use (p+a)h 3bh 07h block status register bit0, block protection bit status active (1=yes) bit1, block lock-down bit status active bit 2, un-lock-down bit bits 3 to 15 reserved for future use (p+b)h 3ch 00h (p+c)h 3dh 33h v dd optimum program/erase voltage conditions (1) (p+d)h 3eh 00h v pp optimum program/erase voltage conditions (1) (p+e)h 3fh 02h otp protection: no. of protection register fields (2) (p+f)h 40h 80h protection sub-register0s start address, least significant bits (80h) (p+10)h 41h 00h protection sub-register0s start address, most significant bits (00h) (p+11)h 42h 03h n where 2 n is number of factory preprogrammed bytes (p+12)h 43h 03h n where 2 n is number of user programmable bytes (p+13)h 44h 89h protection registers1-16s start address, least significant bits (89h) protection registers1-16s start address, most significant bits (00h) least significant bits (00h) in start address of number n of factory programmed protection sub-registers (n = 0) most significant bits (00h) in start address of number n of factory programmed protection sub-registers (n = 0) n where 2 n is the number of factory preprogrammed bytes per protection sub-register least significant bits (10h) in start address of number n of factory programmed protection sub-registers (n = 16) most significant bits (00h) in start address of number of factory programmed protection sub-registers n where 2 n is the number of user programmable bytes per protection sub-register (p+14)h 45h 00h (p+15)h 46h 00h (p+16)h 47h 00h (p+17)h 48h 00h (p+18)h 49h 00h (p+19)h 4ah 00h (p+1a)h 4bh 10h (p+1b)h 4ch 00h (p+1c)h 4dh 04h
53/65 m58lw128h table 31. burst read information offset data description value (p+1d)h = 4eh 04h page-mode read capability bits 0-7 n such that 2 n hex value represents the number of read- page bytes. see offset 28h for device word width to determine page-mode data output width. 16 bytes (p+1e)h = 4fh 02h number of synchronous mode read configuration fields that follow. 2 (p+1f)h = 50h 02h synchronous mode read capability configuration 1 bit 3-7 reserved bit 0-2 n such that 2 n+1 hex value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. a value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the devices burstable address space. this fields 3-bit value can be written directly to the read configuration register bits 0-2 if the device is configured for its maximum word width. see offset 28h for word width to determine the burst data output width. 8 (p+20)h = 51h 03h synchronous mode read capability configuration 2 16
m58lw128h 54/65 appendix c. flowcharts figure 23. write to buffer and program flowchart and pseudo code write to buffer e8h command, block address ai06769 start read status register no sr7 = 1 write buffer data, start address yes x = n yes no end no write to buffer timeout write n (1) , block address yes x = 0 write next buffer data, next program address (2) x = x + 1 program buffer to flash confirm d0h read status register no sr7 = 1 yes full status register check (3) try again later note 1: n+1 is number of words to be programmed note 2: address must be between start address and start address+n. note 3: a full status register check must be done to check the program operation's success.
55/65 m58lw128h figure 24. buffer enhanced factory program flowchart and pseudo code write 80h to address wa1 ai07302 start write d0h to address wa1 write ffffh to address = not wa1 read status register sr7 = 0 no no sr0 = 0 yes read status register sr3 and sr1for errors exit write pdx address wa1 increment count x = x + 1 initialize count x = 0 x = 32 yes read status register last data? yes read status register sr7 = 1 yes full status register check end yes buffer_enhanced_factory_program_command writetoflash (bank_address, 0x80) ; writetoflash (bank_address, 0xd0 ; do status_register=readflash if (status_register.sr7==0) /*exit*/ do status_register=readflash if (status_register.sr4==1 /*error*/ if (status_register.sr1==1 /*locked block*/ if (status_register.sr3==1) /*vpp error*/ else do writetoflash (bank_address, wa1) while x<32 sr4 = 1 no no if x=32 do status_register=readflash while status_register.sr0==1 if sr0==0 do writetoflash (bank_address, wa1) while x<32 writetoflash(another_block_address, ffffh) do status_register=readflash while status_register.sr7==0 if sr7==1; /*full status register check*/ no no setup phase program and verify phase exit phase
m58lw128h 56/65 figure 25. program suspend & resume flowchart and pseudo code write 70h ai00612b read status register yes no sr7 = 1 yes no sr2 = 1 program continues write ffh program/erase suspend command: C write b0h C write 70h do: C read status register while sr7 = 1 if sr2 = 0, program completed read memory array command: C write ffh C one or more data reads from other blocks write d0h program erase resume command: C write d0h to resume erasure C if the program operation completed then this is not necessary. the device returns to read array as normal (as if the program/erase suspend command was not issued). read data from another block start write b0h program complete write ffh read data
57/65 m58lw128h figure 26. erase flowchart and pseudo code note: 1. if an error is found, the status register must be cleared (clear status register command) before further program or eras e opera- tions. write 20h ai006770 start write d0h to block address read status register yes no sr7 = 1 yes no sr3 = 0 no sr4, sr5 = 0 v pen invalid error (1) command sequence error erase command: C write 20h C write d0h to block address (a23-a17) (memory enters read status register after the erase command) do: C read status register C if program/erase suspend command given execute suspend erase loop while sr7 = 1 if sr3 = 1, v pen invalid error: C error handler if sr4, sr5 = 1, command sequence error: C error handler yes no sr5 = 0 erase error (1) yes no suspend suspend loop if sr5 = 1, erase error: C error handler yes end yes no sr1 = 0 erase to protected block error if sr1 = 1, erase to protected block error: C error handler
m58lw128h 58/65 figure 27. erase suspend & resume flowchart and pseudo code write 70h ai00615b read status register yes no sr7 = 1 yes no sr6 = 1 erase continues write ffh program/erase suspend command: C write b0h C write 70h do: C read status register while sr7 = 1 if sr6 = 0, erase completed read memory array command: C write ffh C one or more data reads from other blocks write d0h read data from another block or program start write b0h erase complete write ffh read data program/erase resume command: C write d0h to resume the erase operation C if the program operation completed then this is not necessary. the device returns to read mode as normal (as if the program/erase suspend was not issued).
59/65 m58lw128h figure 28. protection operations flowchart and pseudo code note: 1. any address within the block can equally be used. write 01h, d0h or 2fh, block address (1) ai08328b read block protection status yes no protection change confirmed? start write 60h, block address (1) protection_operation_command (address, protection_operation) { writetoflash (address, 0x60) ; /*configuration setup*/ /* see note (1) */ if (readflash (address) ! = protection_status_expected) error_handler () ; /*check the protection status (see read electronic signature table ) * writetoflash (address, 0xff) ; /*reset to read array mode*/ /*see note (1) */ } write ffh, block address (1) write 90h, block address (1) end if (protection_operation==protect) /*to protect the block*/ writetoflash (address, 0x01) ; else if (protection_operation==unprotect) /*to unprotect the block*/ writetoflash (address, 0xd0) ; else if (protection_operation==lock-down) /*to lock the block*/ writetoflash (address, 0x2f) ; writetoflash (address, 0x90) ; /*see note (1) */
m58lw128h 60/65 figure 29. protection register program flowchart and pseudo code note: pr = protection register write pr address, pr data ai06159b yes no sr7 = 1 start write c0h write ffh read status register pr program sucessful sr1, sr4 = 0,1 v pen invalid error protection register program error protection register program error yes yes yes no no no protection register program command C write c0h C write protection register address, protection register data do: C read status register while sr7 = 1 read memory array command: C write ffh if sr1 = 0, sr4 = 1 protection register program error sr3, sr4 = 1,1 if sr3 = 1, sr4 = 1 v pen invalid error sr1, sr4 = 1,1 if sr1 = 1, sr4 = 1 program error due to protection register protection
61/65 m58lw128h figure 30. command interface and program erase controller flowchart (a) ai06771 read electronic signature yes no 90h read status register yes 70h no clear status register yes 50h no write to buffer and program yes e8h no block erase yes 20h (1) no block erase command error yes ffh wait for command to be written read memory array yes d0h no a b no c read query yes 98h no d0h yes no program command error note 1. the erase command (20h) can only be issued if the flash memory is not already in erase suspend. buffer enhanced factory program yes 80h no d d0h yes no
m58lw128h 62/65 figure 31. command interface and program erase controller flowchart (b) read status register yes no 70h b block erase yes ready ? no a b0h no read status register yes ready ? no erase suspend yes d0h read memory array yes erase suspended read status register (read status register) yes (erase resume) no read status register 90h no read electronic signature yes 98h no read query yes e8h no write to buffer and program yes c ai06772 program/erase controller status bit in the status register read status register d0h yes no no program command error wait for command ffh yes read memory array no buffer enhanced factory program yes last data ? no d
63/65 m58lw128h figure 32. command interface and program erase controller flowchart (c) read status register yes no 70h b program yes ready ? no c b0h no read status register yes ready ? no program suspend yes d0h read memory array yes program suspended read status register (read status register) yes no (program resume) no read status register 90h no read electronic signature yes 98h no read query yes ai08343 program/erase controller status bit in the status register read status register read memory array yes no ffh wait for command
m58lw128h 64/65 revision history table 32. document revision history date version revision details 18-aug-2003 1.0 31-jul-03: first draft. 7-aug-03:second draft t plrh changed to t plrst figure 20 and table 20, reset, power-down and power-up ac waveforms and characteristics modified 8-aug-03: third draft tplrst timing name and definition modified
65/65 m58lw128h information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners ? 2003 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco - singapore - spain - sweden - switzerland - united kingdom - united states www.st.com

▲Up To Search▲

Price & Availability of M58LW128H115ZA1

	To Download M58LW128H115ZA1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .